1. Field of the Invention
The present invention relates to a packaged semiconductor device, and more particularly, to a hermetically sealed ceramic package type semiconductor device and a method of assembling the same.
The number of components (active elements) of a semiconductor chip (IC or LSI chip) continues to increase, and accordingly, the consumption of electric power as the semiconductor chip is increased, and thus more heat is generated thereby. To remove this heat from the semiconductor chip, a ceramic package is provided with a heatsink member (a heatsink plate or a heatsink plate with a heat dissipation fin).
2. Description of the Related Art
A known ceramic package type semiconductor device comprises a ceramic substrate, a semiconductor chip mounted on the substrate with a top face thereof facing downward, a metal cap covering the chip and having a through-hole at a top portion thereof, and a heatsink member bonded to a bottom surface of the chip through the through-hole with a solder. Such a semiconductor device and variations thereof have been proposed in U.S. Pat. Nos. 4,698,663 and 4,742,024, which are based on Japanese Unexamined Patent Publication (Kokai, JP-A) No. 63-73650, and a ceramic package type semiconductor device similar to the proposed semiconductor device is illustrated in FIGS. 1 to 6. FIG. 1 is a front view, FIG. 2 is a plan view, FIG. 3 is a bottom view, and FIG. 4 is a sectional view of the semiconductor device. FIG. 5 is a partial perspective view of the semiconductor device except for a ceramic substrate, and FIG. 6 is a partial enlarged section view of the semiconductor device. The semiconductor device 10 comprises a semiconductor chip (element) 11, a ceramic substrate 12 with pins 20, a metal cap 13, heatsink plate 15a, and a heat dissipation fin 15b. In this case, the ceramic substrate 12 is provided with many pins 20 (FIG. 3) soldered to the bottom surface 12b thereof, i.e., is a pin-grid array (PGA). The ceramic substrate 12 is made of AlN, SiC, Al.sub.2 O.sub.3 or the like, and is provided with a wiring pattern layer 17 on the top surface 12a thereof. The top surface 12a and the layer 17 are covered with a polyimide layer 21, to prevent .alpha.-ray errors (FIGS. 4 and 6). The ceramic substrate 12 is provided with interconnections 18 which connect the wiring pattern layer 17 and the pins 20 and are made of a refractory metal (e.g., tungsten: W) filling via holes.
The semiconductor chip 11 is provided with solder bumps 11c on the top surface 11a thereof (FIGS. 4 and 6) and microleads 19 bonded to the bumps 11c, respectively, by a tape automated bonding (TAB) processing method. Note the semiconductor chip 11 may be a flip-chip having solder bumps without microleads. The semiconductor chip 11 is mounted on the ceramic substrate 12 by bonding the TAB leads 19 to the wiring pattern layer 17.
The metal cap 13 includes a top flat portion 13a and a flange portion 13b and has a through-hole 13c provided in the top portion 13a and having a rectangular (square) size smaller than the external size of the semiconductor chip 11. The metal cap 13- is made of Fe-Ni-Co alloy (e.g., Kovar), Fe-Ni alloy (e.g., 42 alloy) or the like. To join or bond the heatsink plate 15a to the bottom surface 11b of the semiconductor chip 11, the heatsink plate 15a is provided with a projecting portion 15c which fits in the through-hole 13c and has a thickness corresponding to that of the metal cap 13, as shown in FIGS. 4 to 6. The heatsink plate 15a with the projecting portion 15c is made of Mo, Cu, Cu-W, Al, Al-N, SiC or the like. In this case, the heat dissipation fin 15b of Cu or Al is bonded to the heatsink plate 15a with solder (not shown) and comprises concentric disk fins. The heat dissipation fin 15b is generally coated (plated) with an Ni layer for soldering.
After the mounting of the semiconductor chip 11, a solder frame 14 is put on the top surface 12a of the substrate 12, a solder plate 16a larger than the opening size of the through-hole 13c is placed on the bottom surface 11b of the semiconductor chip 11, the flange portion 13b and the top flat portion 13a of the metal cap 13 are placed on the solder frame 14 and the solder plate 16a, respectively, an additional solder frame 16b is put on the top flat portion 13a, and then the projecting portion 15c of the heatsink plate 15a with the fin 15b is placed on the solder plate 16a through the through-hole 13c. The solder frame 14, solder plate 16a and the additional solder frame 16b are made of the same solder, e.g., Pb-Sn. The thus assembled device is then heated to reflow (melt) the solders 14, 16a and 16b, so that the cap 13 is soldered to the substrate 12 and to the heatsink plate 15a, and simultaneously the semiconductor chip 11 is soldered to the both the cap 13 and the projecting portion 15c, whereby a hermetic sealing of the semiconductor, chip is completed.
The additional solder frame 16b is not provided in the above-mentioned U.S. patents.
When the heat treatment for reflowing the solder material is carried out, a portion 16c (FIG. 6) of the solder plate 16a may flow out of a gap between the semiconductor chip 13 and top portion 13a and may drop down on or leach the microleads 19, to thereby cause a short-circuit. If a total thickness of the top portion 13a and additional solder frame 16b is larger than the thickness of the projecting portion 15c, and a space is formed between the projection portion 15c and the solder plate 16a during the heat treatment, the solder plate 16a is too short to completely fill the gap between the projection portion 15c and the bottom surface 11b of the semiconductor chip 11. Accordingly, the whole surface of the projection portion 15c comes into contact with the reflowed solder, and thus the heat transfer effect is reduced. A space exists between the side surface of the top portion 13a of the cap 13 and side surface of the projection portion 15c wherein a preformed solder member is not arranged, and during the heat treatment, a gas flows outwardly from that space to form voids in the reflowed solder layers 16b and 16c, whereby the bonding strength and water vapor barrier properties of the solder layers 16b and 16c are lowered. As shown in FIGS. 4 to 6, the external size of the projection portion 15c is smaller than that of the semiconductor chip 11, and the top portion 13a of the cap 13 comes into contact with the semi-conductor chip 11, and since the metal (e.g., Kovar) of the cap 13 has a smaller heat transfer rate than that of the heatsink plate 15a, the top portion 13a prevents the dissipation of heat from the heating chip 11. Furthermore, during the operation of the semiconductor device 10, the semiconductor chip 11 generates heat to thermally expand the chip itself, the heatsink plate 15a including the projection portion 15c, and the cap 13, and since the heatsink plate 15a is bonded to the top portion 13a with the solder frame (reflowed layer) 16b, the projecting portion 15c can be thermally expanded downward to press against the semiconductor chip 11. This pressure on the chip 11 repeatedly imposes a stress on the microleads (TAB leads) 19, for a long time, and accordingly, the microleads 19 are often broken.